In conventional DRAM arrays, information is stored in a given DRAM cell by driving a wordline (WL) appropriately to activate a transfer transistor, and thereby transfer charge into the cell capacitor. In general, the retention time of the cell, and the performance of the cell, increases with the amount of charge transferred to the cell. The transfer transistor of a given cell is activated for transferring charge into the cell by application of a voltage Vpp to the wordline, and the transfer transistor is switched off by application of a voltage wordline low (WLL) to the wordline.
In order to transfer the maximum possible charge to the cell, Vpp must be greater than the threshold voltage Vt of the transfer transistor. Therefore, Vpp may be the sum of the voltage supply (Vdd) and the transistor threshold voltage (Vtn). Increases in the Vpp voltage permit reductions in the charge transfer time. However, due to reliability concerns, the maximum Vpp is limited due to the maximum allowable electric field across the gate oxide of the transfer transistor. The Vpp voltage may be regulated to assure the gate oxide of the transfer transistor is not damaged. A reference voltage such as a bandgap circuit may produce may be used to aid in this voltage regulation.
A bandgap circuit generates a fixed dc reference voltage that does not change with temperature. A bandgap circuit is based on adding two voltages whose temperature coefficients have opposite signs. With steadily decreasing power supply voltages in CMOS technologies, the design of voltage/current references becomes more difficult. The traditional voltage summing bandgap reference circuit is not suited for a CMOS technology with a maximum supply voltage of 1.0V or less. The value of bandgap voltage in silicon (1.12V) is close to or exceeds the maximum supply voltage admissible in the technology. This causes bandgap circuitry to fail.